Baugh Woolley Multiplier Analysis

2039 Words9 Pages
Abstract- In this paper we have proposed Baugh Wooley Multiplier with carry skip adder. Baugh Wooley multiplier performs an multiplication operation on signed numbers only. Most signal processing application performs truncated multiplication in order to decrease the word size. When direct truncation is used it provides significant savings in power, area, complexity and timing it can also introduces large amount of error in the output. so here in this paper a programmable truncated Baugh Woolley multiplier to enhance the speed and to reduce the critical path delay. The proposed work designed on 8 bit and 16 bit and study also shows the comparison between carry save adder and redesigned the carry skip adder using Baugh Woolley multiplier having…show more content…
BAUGH WOOLEY ALGORITHM Baugh-Wooley multiplier of an Two’s compliment Signed multipliers is an well known algorithm for signed multiplication because it maximizes their regularity of the multiplier and allows all partial products must have positive sign bits [3]. Baugh–Wooley technique was developed to design an direct multipliers for two's compliment numbers [9]. When multiplying two's compliment numbers directly, each of the partial products to be added is a signed numbers. Thus both partial product has to be sign extended to the width of the final product in order to form a exact sum by the Carry Save Adder (CSA) tree. According to Baugh-Woolley approach, an efficient method of adding extra entries to the bit matrix recommended to avoid having deal with the negatively weighted bits in the partial product matrix. The Baugh Woolley algorithm is a relative straightforward way of performing signed multiplications. Demonstrates the algorithm for an 8-bit case, where the partial product array has been reorganized according to the scheme of Hatamian. The formation of the reorganized partial-product array comprises three steps: i)the most important partial product of the first N-1 rows and the last row of partial products except the most significant have to be canceled, ii) a constant one is added to the Nth column, iii) the most significant bit (MSB) of the final result is canceled. Multiplication involves two basic operations: the generation of the partial product and their…show more content…
Figure 1.2 Basic Architecture of MAC Unit In computing, especially digital signal processing, the multiply accumulate operation is a common step that computes the product of two numbers and adds that product to an accumulator. The hardware unit that performs the operation is known as a multiplier accumulator (MAC, or MAC unit); the operation itselfis also often called a MAC or a MAC operation [1].Refer to (2) the MAC operation modifies an accumulator. . E. CARRY SAVE ADDER In Carry Save Adder (CSA), three bits are added parallel at a time. In this method, the carry is not propagated through the stages. Instead, carry is stored in present stage, and updated as addend value in their next stage. Hence, the delay due to the carry is reduced in this scheme. F. CARRY SKIP

More about Baugh Woolley Multiplier Analysis

Open Document