2296 WordsOct 8, 201210 Pages

Design and Characterization of Parallel Prefix Adders using FPGAs
David H. K. Hoe, Chris Martinez and Sri Jyothsna Vundavalli Department of Electrical Engineering The University of Texas, Tyler dhoe@uttyler.edu
Abstract—Parallel-prefix adders (also known as carrytree adders) are known to have the best performance in VLSI designs. However, this performance advantage does not translate directly into FPGA implementations due to constraints on logic block configurations and routing overhead. This paper investigates three types of carry-tree adders (the Kogge-Stone, sparse Kogge-Stone, and spanning tree adder) and compares them to the simple Ripple Carry Adder (RCA) and Carry Skip Adder (CSA). These designs of varied bit-widths were implemented on a Xilinx Spartan 3E FPGA and delay measurements were made with a high-performance logic analyzer. Due to the presence of a fast carry-chain, the RCA designs exhibit better delay performance up to 128 bits. The carry-tree adders are expected to have a speed advantage over the RCA as bit widths approach 256.
described. An efficient testing strategy for evaluating the performance of these adders is discussed. Several tree-based adder structures are implemented and characterized on a FPGA and compared with the Ripple Carry Adder (RCA) and the Carry Skip Adder (CSA). Finally, some conclusions and suggestions for improving FPGA designs to enable better tree-based adder performance are given. II. CARRY-TREE ADDER DESIGNS Parallel-prefix adders, also known as carry-tree adders, pre-compute the propagate and generate signals [1]. These signals are variously combined using the fundamental carry operator (fco) [2]. (gL, pL) ο (gR, pR) = (gL + pL•gR, pL • pR) (1) Due to associative property of the fco, these operators can be combined in different ways to form various adder structures. For, example the four-bit carry-lookahead

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