Input-Output Mapping Techniques Essay

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Chapter 5 Input/Output Organization Jin-Fu Li Department of Electrical Engineering National Central University Jungli, Taiwan Outline Accessing I/O Devices Interrupts Direct Memory Access Buses Interface Circuits Standard I/O Interfaces Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 2 Content Coverage Main Memory System Address Data/Instruction Central Processing Unit (CPU) Operational Registers Cache memory Program Counter Arithmetic and Logic Unit Instruction Sets Control Unit Input/Output System Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 3 Accessing I/O Devices Single-bus structure The bus enables all the devices connected to it to exchange information Typically, the bus consists of three sets of lines used to carry address, data, and control signals Each I/O device is assigned a unique set of addresses Processor Memory Bus I/O device 1 Advanced Reliable Systems (ARES) Lab. I/O device n Jin-Fu Li, EE, NCU 4 I/O Mapping Memory mapped I/O Devices and memory share an address space I/O looks just like memory read/write No special commands for I/O Large selection of memory access commands available Isolated I/O Separate address spaces Need I/O or memory select lines Special commands for I/O Limited set Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 5 Memory-Mapped I/O When I/O devices and the memory share the same address space, the arrangement is called memorymapped I/O With memory-mapped I/O, any machine instruction that can access memory can be used to transfer data to or from an I/O device Most computer systems use memory-mapped I/O. Some processors have special IN and OUT instructions to perform I/O transfers When building a computer system based on these processors, the designer has the option

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