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Brenkung Adder Design Essay

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Below is an essay on "Brenkung Adder Design" from Anti Essays, your source for research papers, essays, and term paper examples.

Executive Summary – Adder Design

The objective of the project is to design a 16-bit adder. The goal of the
project is to minimize the delay while keeping power within constraints, as well
as minimizing the area. The constraints are as follows: Energy/operation has to be less
t trise han t0.5nJ
and fall < 200ps, and use the standard cell layout, which must obey all the
design rules. Throughout the course there were several adder topologies with
different advantages been introduced, and we finally came to the decision to
choose Brent-Kung adder architecture. The reason we chose this topology was
because its implementation was simpler than Radix-4 Kogge-Stone tree. As a
result the layout of the circuit would be less complicated. Even though it is a bit
slower than the Kogg-Stone, it would save us time doing the layout in the end.
After choosing the topology, we had to come up with the logic style to implement the bl
We had implemented the logic blocks using transmission gates to gain more speed. However, for simplicity in sizing the
Since we wanted the adder to operate as fast as possible, we came up with some ideas to minimize the
propagation delay such as: we modified the Brent-Kung tree, added 3 more dot products and cut the number of
stages for the critical path from 7 to 5. For the Brent-Kung tree in order to get the carryout C14, the adder has to
wait for the product of C7&C11, then C11&13 and finally C13&P14. On the other hand for the modified Brent-
Kung tree C7 is directly producted with C13 at the fourth stage. This helps the C14 to be available at the fifth
stage. The modified Brent-Kung tree is shown below as well as the critical path, which is highlighted in red.

Loading estimate:
Cin = 24.7fF(from the sum of all the
gate input capacitance of the very
first stage.)
Since the adder driving a 1.8mm long
bus with 6 loads evenly distributed.
Each capacitive load is equal...

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