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Why Design for Testability
• Reduce test cost
• Improve product quality
• Reduce time to market

DFT Techniques
• Provide for initialization
– Self-initialization
– Avoids long initialization sequences
• Isolate clocks from logic
– ATE controls test speeds, not logic
– Avoid gated clocks
DFT Techniques
• Avoid asynchronous logic
– Hard to generate test patterns and random tests
• Segment design
– Easier to isolate faults
• Add critical test points
– Allows for ICT

What is Testability?
• Testability is a measure of the ease of generating test sets that have high fault coverage – Internal nodes in the circuit must be both controllable and observable What is DFT?
• Design for Testability involves modifying the design and adding extra hardware/software to
make the design more testable
– Target sequential circuits
– Improve faulty coverage
– Reduce test generation time
– Reduce test application time
– Minimize impact on performance and PCB space

To summarize, the basic motivation for boundary scan was the miniaturization of device packaging, the development of surface-mounted packaging, and the associated development of the multi-layer board to accommodate the extra interconnects between the increased density of devices on the board. These factors led to a reduction of the one thing an in-circuit tester requires: physical access for the bed-of-nails probes.
The long-term solution to this reduction in physical probe access was to consider building the access inside the device i.e. a boundary scan register. In the next section, we will take a look at the device-level architecture of a boundary-scan device, and begin to understand how the boundary-scan register solves the limited-access board-test problem.


In a boundary-scan...